/****************************************************************************** SPDX-License-Identifier: BSD-3-Clause Copyright (c) 2001-2020, Intel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the Intel Corporation nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ******************************************************************************/ #ifndef _FREEBSD_OS_H_ #define _FREEBSD_OS_H_ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #define ASSERT(x) if(!(x)) panic("EM: x") #define us_scale(x) max(1, (x/(1000000/hz))) static inline int ms_scale(int x) { if (hz == 1000) { return (x); } else if (hz > 1000) { return (x*(hz/1000)); } else { return (max(1, x/(1000/hz))); } } extern int e1000_use_pause_delay; static inline void safe_pause_us(int x) { if (!e1000_use_pause_delay) { DELAY(x); } else { pause("e1000_delay", max(1, x/(1000000/hz))); } } static inline void safe_pause_ms(int x) { if (!e1000_use_pause_delay) { DELAY(x*1000); } else { pause("e1000_delay", ms_scale(x)); } } #define usec_delay(x) safe_pause_us(x) #define usec_delay_irq(x) usec_delay(x) #define msec_delay(x) safe_pause_ms(x) #define msec_delay_irq(x) msec_delay(x) /* Enable/disable debugging statements in shared code */ #define DBG 0 #define DEBUGOUT(...) \ do { if (DBG) printf(__VA_ARGS__); } while (0) #define DEBUGOUT1(...) DEBUGOUT(__VA_ARGS__) #define DEBUGOUT2(...) DEBUGOUT(__VA_ARGS__) #define DEBUGOUT3(...) DEBUGOUT(__VA_ARGS__) #define DEBUGOUT7(...) DEBUGOUT(__VA_ARGS__) #define DEBUGFUNC(F) DEBUGOUT(F "\n") #define STATIC static #define CMD_MEM_WRT_INVALIDATE 0x0010 /* BIT_4 */ #define PCI_COMMAND_REGISTER PCIR_COMMAND typedef uint64_t u64; typedef uint32_t u32; typedef uint16_t u16; typedef uint8_t u8; typedef int64_t s64; typedef int32_t s32; typedef int16_t s16; typedef int8_t s8; #define __le16 u16 #define __le32 u32 #define __le64 u64 #ifdef INVARIANTS #define ASSERT_CTX_LOCK_HELD(hw) (sx_assert(iflib_ctx_lock_get(((struct e1000_osdep *)hw->back)->ctx), SX_XLOCKED)) #else #define ASSERT_CTX_LOCK_HELD(hw) #endif #if defined(__i386__) || defined(__amd64__) static __inline void prefetch(void *x) { __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); } #else #define prefetch(x) #endif struct e1000_osdep { bus_space_tag_t mem_bus_space_tag; bus_space_handle_t mem_bus_space_handle; #ifdef INVARIANTS bus_size_t mem_bus_space_size; #endif bus_space_tag_t io_bus_space_tag; bus_space_handle_t io_bus_space_handle; bus_space_tag_t flash_bus_space_tag; bus_space_handle_t flash_bus_space_handle; device_t dev; if_ctx_t ctx; bool pcim2pci_arbiter_wa; bool vf; bool vf_82576; }; void e1000_pcim2pci_write(struct e1000_osdep *, uint32_t, uint32_t); #ifdef INVARIANTS /* * 82576 and I350 VFs expose a sparse register file. Keep this list local to * the OS accessors so a PF-only register that leaks into the shared VF path * fails at its first access instead of returning reserved-register garbage. * * The driver intentionally uses only queue pair zero. It also clears the * retained configuration of the unused second 82576 queue pair after VFLR. * Expanding VF data-path queue support must extend this predicate from the * applicable device CSR map. */ static __inline bool e1000_vf_reg_valid(uint32_t reg, bool write, bool vf_82576) { /* VF mailbox memory: 16 dwords beginning at 0x800. */ if (reg >= 0x00800 && reg <= 0x0083c && (reg & 3) == 0) return (true); /* The three VF MSI-X interrupt-throttling registers. */ if (reg >= 0x01680 && reg <= 0x01688 && (reg & 3) == 0) return (true); /* Receive queue zero. */ switch (reg) { case 0x02800: /* RDBAL */ case 0x02804: /* RDBAH */ case 0x02808: /* RDLEN */ case 0x0280c: /* SRRCTL */ case 0x02810: /* RDH */ case 0x02814: /* RXCTL */ case 0x02818: /* RDT */ case 0x02828: /* RXDCTL */ return (true); } /* Transmit queue zero. */ switch (reg) { case 0x03800: /* TDBAL */ case 0x03804: /* TDBAH */ case 0x03808: /* TDLEN */ case 0x03810: /* TDH */ case 0x03814: /* TXCTL */ case 0x03818: /* TDT */ case 0x03828: /* TXDCTL */ case 0x03838: /* TDWBAL */ case 0x0383c: /* TDWBAH */ return (true); } /* Retained configuration from 82576 virtual queue one. */ if (vf_82576) { switch (reg) { case 0x0290c: /* SRRCTL(1) */ case 0x02914: /* RXCTL(1) */ case 0x02928: /* RXDCTL(1) */ case 0x03914: /* TXCTL(1) */ case 0x03928: /* TXDCTL(1) */ case 0x03938: /* TDWBAL(1) */ case 0x0393c: /* TDWBAH(1) */ return (true); } } /* * 82576 exposes VFMPRC at 0xf3c. I350 erratum 31 makes * its corrected 0xf38 address inaccessible to a VF. */ if (vf_82576 && reg == 0x00f3c) return (!write); switch (reg) { case 0x00000: /* CTRL */ case 0x000c4: /* Legacy ITR, listed but unused by igb VFs */ case 0x00c40: /* V2PMAILBOX(0) */ case 0x00f0c: /* VFPSRTYPE */ case 0x01524: /* EIMS */ case 0x0152c: /* EIAC */ case 0x01530: /* EIAM */ case 0x01700: /* IVAR0 */ case 0x01740: /* IVAR_MISC */ return (true); case 0x01520: /* EICS */ case 0x01528: /* EIMC */ return (write); case 0x00008: /* STATUS */ case 0x00f10: /* VFGPRC */ case 0x00f14: /* VFGPTC */ case 0x00f18: /* VFGORC */ case 0x00f34: /* VFGOTC */ case 0x00f40: /* VFGPRLBC */ case 0x00f44: /* VFGPTLBC */ case 0x00f48: /* VFGORLBC */ case 0x00f50: /* VFGOTLBC */ case 0x01580: /* EICR */ return (!write); default: return (false); } } #endif #define E1000_REGISTER(hw, reg) (((hw)->mac.type >= e1000_82543) \ ? reg : e1000_translate_register_82542(reg)) #define E1000_WRITE_FLUSH(a) E1000_READ_REG(a, E1000_STATUS) /* Read from an absolute offset in the adapter's memory space */ #define E1000_READ_OFFSET(hw, offset) \ bus_space_read_4(((struct e1000_osdep *)(hw)->back)->mem_bus_space_tag, \ ((struct e1000_osdep *)(hw)->back)->mem_bus_space_handle, offset) static __inline uint32_t e1000_rd32(struct e1000_osdep *osdep, uint32_t reg) { KASSERT(reg < osdep->mem_bus_space_size, ("e1000: register offset %#jx too large (max is %#jx)", (uintmax_t)reg, (uintmax_t)osdep->mem_bus_space_size)); #ifdef INVARIANTS KASSERT(!osdep->vf || e1000_vf_reg_valid(reg, false, osdep->vf_82576), ("e1000: invalid VF register read at %#x", reg)); #endif return (bus_space_read_4(osdep->mem_bus_space_tag, osdep->mem_bus_space_handle, reg)); } static __inline void e1000_wr32(struct e1000_osdep *osdep, uint32_t reg, uint32_t value) { KASSERT(reg < osdep->mem_bus_space_size, ("e1000: register offset %#jx too large (max is %#jx)", (uintmax_t)reg, (uintmax_t)osdep->mem_bus_space_size)); #ifdef INVARIANTS KASSERT(!osdep->vf || e1000_vf_reg_valid(reg, true, osdep->vf_82576), ("e1000: invalid VF register write at %#x", reg)); #endif if (__predict_true(!osdep->pcim2pci_arbiter_wa)) { bus_space_write_4(osdep->mem_bus_space_tag, osdep->mem_bus_space_handle, reg, value); return; } e1000_pcim2pci_write(osdep, reg, value); } /* Write to an absolute offset in the adapter's memory space. */ #define E1000_WRITE_OFFSET(hw, offset, value) \ e1000_wr32((hw)->back, (offset), (value)) /* Register READ/WRITE macros */ #define E1000_READ_REG(hw, reg) \ e1000_rd32((hw)->back, E1000_REGISTER(hw, reg)) #define E1000_WRITE_REG(hw, reg, value) \ e1000_wr32((hw)->back, E1000_REGISTER(hw, reg), value) #define E1000_READ_REG_ARRAY(hw, reg, index) \ e1000_rd32((hw)->back, E1000_REGISTER(hw, reg) + ((index) << 2)) #define E1000_WRITE_REG_ARRAY(hw, reg, index, value) \ e1000_wr32((hw)->back, E1000_REGISTER(hw, reg) + ((index) << 2), value) #define E1000_READ_REG_ARRAY_DWORD E1000_READ_REG_ARRAY #define E1000_WRITE_REG_ARRAY_DWORD E1000_WRITE_REG_ARRAY #define E1000_READ_REG_ARRAY_BYTE(hw, reg, index) \ bus_space_read_1(((struct e1000_osdep *)(hw)->back)->mem_bus_space_tag, \ ((struct e1000_osdep *)(hw)->back)->mem_bus_space_handle, \ E1000_REGISTER(hw, reg) + index) #define E1000_WRITE_REG_ARRAY_BYTE(hw, reg, index, value) \ bus_space_write_1(((struct e1000_osdep *)(hw)->back)->mem_bus_space_tag, \ ((struct e1000_osdep *)(hw)->back)->mem_bus_space_handle, \ E1000_REGISTER(hw, reg) + index, value) #define E1000_WRITE_REG_ARRAY_WORD(hw, reg, index, value) \ bus_space_write_2(((struct e1000_osdep *)(hw)->back)->mem_bus_space_tag, \ ((struct e1000_osdep *)(hw)->back)->mem_bus_space_handle, \ E1000_REGISTER(hw, reg) + (index << 1), value) #define E1000_WRITE_REG_IO(hw, reg, value) do {\ bus_space_write_4(((struct e1000_osdep *)(hw)->back)->io_bus_space_tag, \ ((struct e1000_osdep *)(hw)->back)->io_bus_space_handle, \ (hw)->io_base, reg); \ bus_space_write_4(((struct e1000_osdep *)(hw)->back)->io_bus_space_tag, \ ((struct e1000_osdep *)(hw)->back)->io_bus_space_handle, \ (hw)->io_base + 4, value); } while (0) #define E1000_READ_FLASH_REG(hw, reg) \ bus_space_read_4(((struct e1000_osdep *)(hw)->back)->flash_bus_space_tag, \ ((struct e1000_osdep *)(hw)->back)->flash_bus_space_handle, reg) #define E1000_READ_FLASH_REG16(hw, reg) \ bus_space_read_2(((struct e1000_osdep *)(hw)->back)->flash_bus_space_tag, \ ((struct e1000_osdep *)(hw)->back)->flash_bus_space_handle, reg) #define E1000_WRITE_FLASH_REG(hw, reg, value) \ bus_space_write_4(((struct e1000_osdep *)(hw)->back)->flash_bus_space_tag, \ ((struct e1000_osdep *)(hw)->back)->flash_bus_space_handle, reg, value) #define E1000_WRITE_FLASH_REG16(hw, reg, value) \ bus_space_write_2(((struct e1000_osdep *)(hw)->back)->flash_bus_space_tag, \ ((struct e1000_osdep *)(hw)->back)->flash_bus_space_handle, reg, value) #if defined(INVARIANTS) #include #define ASSERT_NO_LOCKS() \ do { \ int unknown_locks = curthread->td_locks - mtx_owned(&Giant); \ if (unknown_locks > 0) { \ WITNESS_WARN(WARN_GIANTOK|WARN_SLEEPOK|WARN_PANIC, NULL, "unexpected non-sleepable lock"); \ } \ MPASS(curthread->td_rw_rlocks == 0); \ MPASS(curthread->td_lk_slocks == 0); \ } while (0) #else #define ASSERT_NO_LOCKS() #endif #endif /* _FREEBSD_OS_H_ */