.\"
.\" SPDX-License-Identifier: BSD-2-Clause
.\"
.\" Copyright (c) 2026 Abdelkader Boudih <seuros@FreeBSD.org>
.\"
.Dd September 7, 2026
.Dt INTEL_PMC 4
.Os
.Sh NAME
.Nm intel_pmc
.Nd Intel Performance Management Controller driver
.Sh SYNOPSIS
.Cd "device intel_pmc"
.Sh DESCRIPTION
The
.Nm
driver exposes information and controls from the Performance
Management Controller (PMC) of Intel platforms.
Presently, it supports the Intel Sunrise Point platform (Skylake CPU
generation), providing access to debug information and controls
related to S0ix (Modern Standby).
.Pp
The cumulative time spent in low power mode while in S0 is reported,
and the administrator can force the platform to ignore IP blocks
whose Latency Tolerance Reporting (LTR) prevents the platform from
entering S0ix.
.Sh HARDWARE
The
.Nm
driver supports the PMC block found in the following Intel Platform
Controller Hubs:
.Pp
.Bl -bullet -compact
.It
Intel Sunrise Point-LP PMC (6th/7th Gen Core mobile, PCI ID 0x8086:0x9d21)
.It
Intel Sunrise Point-H PMC (6th/7th Gen Core desktop/server,
PCI ID 0x8086:0xa121)
.El
.Sh SYSCTLS
The following
.Xr sysctl 8
variables are available:
.Bl -tag -width indent
.It Va dev.intel_pmc.%d.ltr_ignore Pq read-write
Latency Tolerance Reporting (LTR) ignore mask.
Each bit corresponds to one IP block (bits 0-16).
Setting a bit tells the PMC to ignore that IP's LTR requirements,
allowing S0ix entry even if the IP would otherwise block it.
A clear bit means the IP's requirements are considered and can
prevent S0ix.
.Pp
Sunrise Point bit assignments:
SOUTHPORT_A, SOUTHPORT_B, SATA, GIGABIT_ETHERNET, XHCI, reserved,
ME, EVA, SOUTHPORT_C, HD_AUDIO, LPSS, SOUTHPORT_D, SOUTHPORT_E,
CAMERA, ESPI, SCC, ISH.
.It Va dev.intel_pmc.%d.slp_s0_residency Pq read-only
Cumulative time in microseconds that the SLP_S0 signal has been
asserted (100\ us per counter step).
Per the datasheet, SLP_S0 asserts when the PCH is idle and the
processor is in C10 state.
A value that never advances indicates S0ix transitions are not occurring.
.Pp
The counter is 32-bit and wraps after approximately 5 days of
cumulative S0ix residency.
.El
.Sh SEE ALSO
.Xr acpi 4 ,
.Xr pci 4 ,
.Xr sysctl 8
.Pp
Intel 100 Series Chipset Family PCH Datasheet, Volume 2, Section 4.3.
.Sh HISTORY
The
.Nm
driver first appeared in
.Fx 16.0 .
.Sh AUTHORS
.An Abdelkader Boudih Aq Mt seuros@FreeBSD.org
.Sh CAVEATS
Only Sunrise Point PCH is supported.
Other PCH generations (Cannon Point, Tiger Lake, etc.) have different
register layouts and are not handled by this driver.